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* The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
74HC/HCT40105 4-bit x 16-word FIFO register
Product specification Supersedes data of December 1990 File under Integrated Circuits, IC06 1998 Jan 23
Philips Semiconductors
Product specification
4-bit x 16-word FIFO register
FEATURES * Independent asynchronous inputs and outputs * Expandable in either direction * Reset capability * Status indicators on inputs and outputs * 3-state outputs * Output capability: standard * ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT40105 are high-speed Si-gate CMOS devices and are pin compatible with the "40105" of the "4000B" series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT40105 are first-in/first-out (FIFO) "elastic" storage registers that can store sixteen 4-bit words. The "40105" is capable of handling input and output data at QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns
74HC/HCT40105
different shifting rates. This feature makes it particularly useful as a buffer between asynchronous systems. Each word position in the register is clocked by a control flip-flop, which stores a marker bit. A "1" signifies that the position's data is filled and a "0" denotes a vacancy in that position. The control flip-flop detects the state of the preceding flip-flop and communicates its own status to the succeeding flip-flop. When a control flip-flop is in the "0" state and sees a "1" in the preceding flip-flop, it generates a clock pulse that transfers data from the preceding four data latches into its own four data latches and resets the preceding flip-flop to "0". The first and last control flip-flops have buffered outputs. Since all empty locations "bubble" automatically to the input end, and all valid data ripples through to the output end, the status of the first control flip-flop (data-in ready output - DIR) indicates if the FIFO is full, and the status of the last flip-flop (data-out ready output - DOR) indicates if the FIFO contains data. As the earliest data is removed from the bottom of the data stack (output end), all data entered later will automatically ripple toward the output.
TYP. SYMBOL tPHL/ tPLH PARAMETER propagation delay MR to DIR, DOR SO to Qn tPHL propagation delay SI to DIR SO to DOR fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz. fo = output frequency in MHz. (CL x VCC2 x fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 maximum clock frequency input capacitance power dissipation capacitance per package notes 1 and 2 16 17 33 3.5 134 18 18 31 3.5 145 ns ns MHz pF pF CONDITIONS HC CL = 15 pF; VCC = 5 V 16 37 15 35 ns ns HCT UNIT
1998 Jan 23
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Philips Semiconductors
Product specification
4-bit x 16-word FIFO register
ORDERING INFORMATION PACKAGE TYPE NUMBER NAME 74HC(T)40105N 74HC(T)40105D 74HC(T)40105DB 74HC(T)40105PW PIN DESCRIPTION PIN NO. 1 2 3 4, 5, 6, 7 8 9 13, 12, 11, 10 14 15 16 SYMBOL OE DIR SI D0 to D3 GND MR Q0 to Q3 DOR SO VCC NAME AND FUNCTION output enable input (active LOW) data-in ready output DIP16 SO16 SSOP16 TSSOP16 DESCRIPTION
74HC/HCT40105
VERSION SOT38-1 SOT109-1 SOT338-1 SOT403-1
plastic dual in-line package; 16 leads (300 mil); long body plastic small outline package; 16 leads; body width 3.9 mm plastic shrink small outline package; 16 leads; body width 5.3 mm plastic thin shrink small outline package; 16 leads; body width 4.4 mm
shift-in input (LOW-to-HIGH, edge-triggered) parallel data inputs ground (0 V) asynchronous master reset input (active HIGH) 3-state data outputs data-out ready output shift-out input (HIGH-to-LOW, edge-triggered) positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
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Philips Semiconductors
Product specification
4-bit x 16-word FIFO register
INPUT AND OUTPUTS Data inputs (D0 to D3) As there is no weighting of the inputs, any input can be assigned as the MSB. The size of the FIFO memory can be reduced from the 4 x 16 configuration, i.e. 3 x 16, down to 1 x 16, by tying unused data input pins to VCC or GND. Data outputs (Q0 to Q3) As there is no weighting of the outputs, any output can be assigned as the MSB. The size of the FIFO memory can be reduced from the 4 x 16 configuration as described for data inputs. In a reduced format, the unused data outputs pins must be left open circuit. Master-reset (MR) When MR is HIGH, the control functions within the FIFO are cleared, and date content is declared invalid. The data-in ready (DIR) flag is set HIGH and the data-out-ready (DOR) flag is set LOW. The output stage remains in the state of the last word that was shifted out, or in the random state existing at power-up. Status flag outputs (DIR, DOR) Indication of the status of the FIFO is given by two status flags, data-in-ready (DIR) and data-out-ready (DOR): DIR = HIGH indicates the input stage is empty and ready to accept valid data; DIR = LOW indicates that the FIFO is full or that a previous shift-in operation is not complete (busy); DOR = HIGH assures valid data is present at the outputs Q0 to Q3 (does not indicate that new data is awaiting transfer into the output stage); DOR = LOW indicates the output stage is busy or there is no valid data. 1998 Jan 23 Shift-in control (SI) Data is loaded into the input stage on a LOW-to-HIGH transition of SI. It also triggers an automatic data transfer process (ripple through). If SI is held HIGH during reset, data will be loaded at the falling edge of the MR signal. Shift-out control (SO) A HIGH-to-LOW transition of SO causes the DOR flags to go LOW. A HIGH-to-LOW transition of SO causes upstream data to move into the output stage, and empty locations to move towards the input stage (bubble-up). Output enable (OE) The outputs Q0 to Q3 are enabled when OE = LOW. When OE = HIGH the outputs are in the high impedance OFF-state. FUNCTIONAL DESCRIPTION Data input Following power-up, the master-reset (MR) input is pulsed HIGH to clear the FIFO memory (see Fig.8). The data-in-ready flag (DIR = HIGH) indicates that the FIFO input stage is empty and ready to receive data. When DIR is valid (HIGH), data present at D0 to D3 can be shifted-in using the SI control input. With SI = HIGH, data is shifted into the input stage and a busy indication is given by DIR going LOW. The data remains at the first location in the FIFO until DIR is set to HIGH and data moves through the FIFO to the output stage, or to the last empty location. If the FIFO is not full after the SI pulse, DIR again becomes valid (HIGH) to indicate that space is available in the FIFO. The DIR flag remains LOW if the FIFO is full (see Fig.6). The SI use must be made
74HC/HCT40105
LOW in order to complete the shift-in process. With the FIFO full, SI can be held HIGH until a shift-out (SO) pulse occurs. Then, following a shift-out of data, an empty location appears at the FIFO input and DIR goes HIGH to allow the next data to be shifted-in. This remains at the first FIFO location until SI goes LOW (see Fig.7). Data transfer After data has been transferred from the input stage of the FIFO following SI = LOW, data moves through the FIFO asynchronously and is stacked at the output end of the register. Empty locations appear at the input end of the FIFO as data moves through the device. Data output The data-out-ready flag (DOR = HIGH) indicates that there is valid data at the output (Q0 to Q3). The initial master-reset at power-on (MR = HIGH) sets DOR to LOW (see Fig.8). After MR = LOW, data shifted into the FIFO moves through to the output stage causing DOR to go HIGH. As the DOR flag goes HIGH, data can be shifted-out using the SO = HIGH, data in the output stage is shifted out and a busy indication is given by DOR going LOW. When SO is made LOW, data moves through the FIFO to fill the output stage and an empty location appears at the input stage. When the output stage is filled DOR goes HIGH, but if the last of the valid data has been shifted-out leaving the FIFO empty the DOR flag remains LOW (see Fig.9). With the FIFO empty, the last word that was shifted-out is latched at the output Q0 to Q3. With the FIFO empty, the SO input can be held HIGH until the SI control input is used. Following an SI pulse,
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Philips Semiconductors
Product specification
4-bit x 16-word FIFO register
data moves through the FIFO to the output stage, resulting in the DOR flag pulsing HIGH and a shift-out of data occurring. The SO control must be made LOW before additional data can be shifted-out (see Fig.10). High-speed burst mode If it is assumed that the shift-in/shift-out pulses are not applied until the respective status flags are valid, it follows that the shift-in/shift-out rates are determined by the status flags. However, without the status flags a high-speed burst mode can be implemented. In this mode, the burst-in/ burst-out rates are determined by the pulse widths of the shift-in/shift-out inputs and burst rates of 35 MHz can be obtained. Shift pulses can be applied without regard to the status flags but shift-in pulses that would overflow the storage capacity of the FIFO are not allowed (see Figs 11 and 12). Expanded format With the addition of a logic gate, the FIFO is easily expanded to increase word length (see Fig.17). The basic operation and timing are identical to a single FIFO, with the exception of an additional gate delay on the flag outputs. If during application, the following occurs: * SI is held HIGH when the FIFO is empty, some additional logic is required to produce a composite DIR pulse (see Figs 7 and 18).
74HC/HCT40105
Due to the part-to-part spread of the ripple through time, the SI signals of FIFOA and FIFOB will not always coincide and the AND-gate will not produce a composite flag signal. The solution is given in Fig.18. The "40105" is easily cascaded to increase the word capacity and no external components are needed. In the cascaded configuration, all necessary communications and timing are performed by the FIFOs. The intercommunication speed is determined by the minimum flag pulse widths and the flag delays. The data rate of cascaded devices is typically 25 MHz. Word-capacity can be expanded to and beyond 32-words x 4-bits (see Fig.19).
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Philips Semiconductors
Product specification
4-bit x 16-word FIFO register
74HC/HCT40105
Fig.4 Functional diagram.
(see control flip-flops) (1) LOW on S input of FF1, and FF5 will set Q output to HIGH independent of state on R input. (2) LOW on R input of FF2, FF3 and FF4 will set Q output to LOW independent of state on S input.
Fig.5 Logic diagram.
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Philips Semiconductors
Product specification
4-bit x 16-word FIFO register
DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tf = tf = 6 ns; CL = 50 pF Tamb (C) 74HC SYMBOL PARAMETER +25 -40 to +85 -40 to +125 min. max. 265 53 45 315 63 54 315 63 54 600 120 102 3000 600 510 3750 750 638 225 45 38 210 42 36 110 22 19 120 24 20
74HC/HCT40105
TEST CONDITIONS UNIT VCC WAVEFORMS
(V)
min. typ. max. min. max. tPHL/ tPLH propagation delay MR to DIR, DOR 52 19 15 tPHL propagation delay SI to DIR 52 19 15 tPHL propagation delay SO to DOR 55 20 16 tPHL/ tPLH propagation delay SO to Qn propagation delay/ ripple through delay SI to DOR propagation delay/ bubble-up delay SO to DIR 3-state output enable time OE to Qn 3-state output disable time OE to Qn output transition time 116 42 34 tPLH 564 205 165 701 255 204 41 15 12 tPHZ/ tPLZ 41 15 12 19 7 6 tW SI pulse width HIGH or LOW 80 16 14 1998 Jan 23 19 7 6 7 175 35 30 210 42 36 210 42 36 400 80 68 2000 400 340 2500 500 425 150 30 26 140 28 24 75 15 13 100 20 17 220 44 37 265 53 45 265 53 45 500 100 85 2500 500 425 3125 625 532 190 38 33 175 35 30 95 19 16
ns
2.0 Fig.8 4.5 6.0
ns
2.0 Fig.6 4.5 6.0
ns
2.0 Fig.9 4.5 6.0
ns
2.0 Fig.14 4.5 6.0
ns
2.0 Fig.10 4.5 6.0
tPLH
ns
2.0 Fig.7 4.5 6.0
tPZH/ tPZL
ns
2.0 Fig.16 4.5 6.0
ns
2.0 Fig.16 4.5 6.0
tTHL/ tTLH
ns
2.0 Fig.14 4.5 6.0
ns
2.0 Fig.6 4.5 6.0
Philips Semiconductors
Product specification
4-bit x 16-word FIFO register
74HC/HCT40105
Tamb (C) 74HC SYMBOL PARAMETER +25 -40 to +85 -40 to +125 min. 180 36 31 225 45 38 215 43 37 10 5 4 10 5 4 120 24 20 75 15 13 -5 -5 -5 190 38 32 2.4 12 14 2.4 12 14 MHz MHz ns ns ns 270 54 46 255 51 43 ns ns ns max. ns
TEST CONDITIONS UNIT VCC WAVEFORMS
(V)
min. typ. max. min. max. tW SO pulse width HIGH or LOW 120 24 20 tW DIR pulse width HIGH 12 6 5 tW DOR pulse width LOW 12 6 5 tW MR pulse width HIGH 80 16 14 trem removal time MR to SI 50 10 9 tsu set-up time Dn to SI hold time Dn to SI maximum pulse frequency SI, SO using flags or burst mode maximum pulse frequency SI, SO cascaded -5 -5 -5 th 125 25 21 fmax 3.6 18 21 3.6 18 21 39 14 11 58 21 17 55 20 16 22 8 6 14 5 4 -39 -14 -11 44 16 13 10 30 36 10 30 36 180 36 31 170 34 29 150 30 26 10 5 4 10 5 4 100 20 17 65 13 11 -5 -5 -5 155 31 26 2.8 14 16 2.8 14 16
2.0 Fig.9 4.5 6.0 2.0 Fig.7 4.5 6.0 2.0 Fig.9 4.5 6.0 2.0 Fig.8 4.5 6.0 2.0 Fig.15 4.5 6.0 2.0 Fig.13 4.5 6.0 2.0 Fig.13 4.5 6.0 2.0 Fig.6, 9, 11 4.5 and 12 6.0 2.0 Figs 6 and 9 4.5 6.0
fmax
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Philips Semiconductors
Product specification
4-bit x 16-word FIFO register
DC CHARACTERISTICS FOR 74HCT For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI
74HC/HCT40105
Note to HCT types The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT OE SI Dn MR SO UNIT LOAD COEFFICIENT 0.75 0.40 0.30 1.50 0.40
AC CHARACTERISTICS FOR 74HCT GND = 0 V; tf = tf = 6 ns; CL = 50 pF Tamb (C) 74HCT SYMBOL PARAMETER +25 -40 to +85 -40 to +125 UNIT VCC WAVEFORMS
(V)
TEST CONDITIONS
min. typ. max. min. max. min. max. tPHL/ tPLH tPHL tPHL tPHL/ tPLH tPLH propagation delay MR to DIR, DOR propagation delay SI to DIR propagation delay SO to DOR propagation delay SO to Qn propagation delay/ ripple through delay SI to DOR propagation delay/ bubble-up delay SO to DIR 3-state output enable time OE to Qn 3-state output disable time OE to Qn output transition time 18 21 20 40 188 35 42 42 80 400 44 53 53 100 500 53 63 63 120 600 ns ns ns ns ns 4.5 Fig.8 4.5 Fig.6 4.5 Fig.9 4.5 Fig.14 4.5 Fig.10
tPLH
244
500
625
750
ns
4.5 Fig.7
tPZH/ tPZL tPHZ/ tPLZ
18 15
35 30
44 38
53 45
ns ns
4.5 Fig.16 4.5 Fig.16
tTHL/ tTLH
7
15
19
22
ns
4.5 Fig.14
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Philips Semiconductors
Product specification
4-bit x 16-word FIFO register
74HC/HCT40105
Tamb (C) 74HCT SYMBOL PARAMETER +25 -40 to +85 -40 to +125
TEST CONDITIONS UNIT VCC WAVEFORMS
(V)
min. typ. max. min. max. min. max. tW tW tW tW tW trem tsu th fmax SI pulse width HIGH or LOW SO pulse width HIGH or LOW DIR pulse width HIGH or LOW DOR pulse width HIGH or LOW MR pulse width HIGH removal time MR to SI set-up time Dn to SI hold time Dn to SI maximum pulse frequency SI, SO using flags or burst mode maximum pulse frequency SI, SO cascaded 16 16 6 6 16 15 -5 27 6 7 20 19 7 7 -14 16 28 34 34 20 20 5 5 20 19 -4 34 12 43 43 24 24 5 5 24 22 -4 41 10 51 51 ns ns ns ns ns ns ns ns MHz 4.5 Fig.6 4.5 Fig.9 4.5 Fig.7 4.5 Fig.9 4.5 Fig.8 4.5 Fig.15 4.5 Fig.13 4.5 Fig.13 4.5 Fig.6, 9, 11 and 12 4.5 Figs 6 and 9
fmax
28
12
10
MHz
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Philips Semiconductors
Product specification
4-bit x 16-word FIFO register
AC WAVEFORMS Shifting in sequence FIFO empty to FIFO full
74HC/HCT40105
Notes to Fig.6 1. DIR initially HIGH; FIFO is prepared for valid data. 2. SI set HIGH; data loaded into input stage. 3. DIR drops LOW, input stage "busy". 4. DIR goes HIGH, status flag indicates FIFO prepared for additional data; data from first location "ripple through". 5. SI set LOW; necessary to complete shift-in process. 6. Repeat process to load 2nd word through to 16th word into FIFO. 7. DIR remains LOW: with attempt to shift into full FIFO, no data transfer occurs.
(1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.6
Waveforms showing the SI input to DIR output propagation delay. The SI pulse width and SI maximum pulse frequency.
With FIFO full; SI held HIGH in anticipation of empty location Notes to Fig.7 1. FIFO is initially, shift-in is held HIGH. 2. SO pulse; data in the output stage is unloaded, "bubble-up process of empty locations begins". 3. DIR HIGH; when empty location reached input stage, flag indicates FIFO is prepared for data input. 4. DIR returns to LOW; FIFO is full again. 5. SI brought LOW; necessary to complete whidt-in process, DIR remains LOW, because FIFO is full.
(1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.7
Waveforms showing bubble-up delay, SO input to DIR output and DIR output pulse width.
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Philips Semiconductors
Product specification
4-bit x 16-word FIFO register
Master reset applied with FIFO full
74HC/HCT40105
Notes to Fig.8 1. DIR LOW, output ready HIGH; assume FIFO is full. 2. MR pulse HIGH; clears FIFO. 3. DIR goes HIGH; flag indicates input prepared for valid data. 4. DOR drops LOW; flag indicates FIFO empty.
(1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.8
Waveforms showing the MR input to DIR, DOR output propagation delays and the MR pulse width.
Shifting out sequence; FIFO full to FIFO empty Notes to Fig.9 1. DOR HIGH; no data transfer in progress, valid data is present at output stage. 2. SO set HIGH. 3. SO is set LOW; data in the input stage is unloaded, and new data replaces it as empty location "bubbles-up" to input stage. 4. DOR drops LOW; output stage "busy". 5. DOR goes HIGH; transfer process completed, valid data present at output after the specified propagation delay.
(1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V.
6. Repeat process to unloaded the 3rd through to the 16th word from FIFO. 7. DOR remains LOW; FIFO is empty.
Fig.9
Waveforms showing the SO input to DIR output propagation delay. The SO pulse width and SO maximum pulse frequency.
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Philips Semiconductors
Product specification
4-bit x 16-word FIFO register
With FIFO empty; SO is held HIGH in anticipation
74HC/HCT40105
Notes to Fig.10
agewidth
SI INPUT
2
VM
(1)
1. FIFO is initially empty, SO is held HIGH. 2. SI pulse; loads data into FIFO and initiates ripple through process.
SO INPUT
1
VM (1)
5
3. DOR flag signals the arrival of valid data at the output stage.
tPHL
t PLH ripple through delay DOR OUTPUT 4 VM
(1)
6
t PHL / t PLH Q n OUTPUT 3
MBA337
4. Output transition; data arrives at output stage after the specified propagation delay between the rising edge of the DOR pulse to the Qn output. 5. SO set LOW; necessary to complete shift-out process. DOR remains LOW, because FIFO is empty. 6. DOR goes LOW; FIFO is empty again.
(1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.10 Waveforms showing ripple through delay SI input to DOR output and propagation delay from the DOR pulse to the Qn output.
Shift-in operation; high-speed burst mode Note to Fig.11 In the high-speed mode, the burst-in rate is determined by the minimum shift-in HIGH and shift-in LOW specifications. The DIR status flag is a don't care condition, and a shift-in pulse can be applied regardless of the flag. A SI pulse which would overflow the storage capacity of the FIFO is ignored.
(1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.11 Waveforms showing SI minimum pulse width and SI maximum pulse frequency, in high-speed shift-in burst mode.
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Product specification
4-bit x 16-word FIFO register
Shift-out operation; high-speed burst mode
74HC/HCT40105
In the high-speed mode, the burst-out rate is determined by the minimum shift-out HIGH and shift-out LOW specifications. The DOR flag is a don't care condition and a SO pulse can be applied without regard to the flag. (1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.12 Waveforms showing SO minimum pulse width and maximum pulse frequency, in high-speed shift-out burst mode.
The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.13 Waveforms showing hold and set up times for Dn input to SI input.
(1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.14 Waveforms showing SO input to Qn output propagation delays and output transition time.
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Product specification
4-bit x 16-word FIFO register
74HC/HCT40105
handbook, halfpage
MR INPUT t rem
V M (1)
SI INPUT
VM
(1)
MBA332
(1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.15 Waveforms showing the MR input to SI input removal time.
(1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.16 Waveforms showing the 3-state enable and disable times for input OE.
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Product specification
4-bit x 16-word FIFO register
APPLICATION INFORMATION
74HC/HCT40105
The PC74HC/HCT40105 is easily expanded to increase word length. Composite DIR and DOR flags are formed with the addition of an AND gate. The basic operation and timing are identical to a single FIFO, with the exception of an added gate delay on the flags.
Fig.17 Expanded FIFO for increased word length; 16 words x 8 bits.
This circuit is only required if the SI input is constantly held HIGH, when the FIFO is empty and the automatic shift-in cycles are started (see Fig.7).
Fig.18 Expanded FIFO for increased word length.
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Philips Semiconductors
Product specification
4-bit x 16-word FIFO register
Expanded format
74HC/HCT40105
Fig.19 shows two cascaded FIFOs providing a capacity of 32 words x 4 bits Fig.20 shows the signals on the nodes of both FIFOs after the application of a SI pulse, when both FIFOs are initially empty. After a rippled through delay, date arrives at the output of FIFOA. Due to SOA being HIGH, a DOR pulse is generated. The requirements of SIB and DnB are satisfied by the DORA pulse width and the timing between the rising edge of DORA and QnA. After a second ripple through delay, data arrives at the output of FIFOB. Fig.21 shows the signals on the nodes of both FIFOs after the application of a SOR pulse, when both FIFOs are initially full. After a bubble-up delay a DIRR pulse is generated, which acts as a SOA pulse for FIFOA. One word is transferred from the output of FIFOA to the input of FIFOB. The requirements of the SOA pulse for FIFOA is satisfied by the pulse width of DORB. After a second bubble-up delay an empty space arrives at DnA, at which time DIRA goes HIGH. Fig.22 shows the waveforms at all external nodes of both FIFOs during a complete shift-in and shift-out sequence.
The PC7HC/HCT40105 is easily cascaded to increase word capacity without any external circuitry. In cascaded format, all necessary communications are handled by the FIFOs. Figs 17 and 19 demonstrate the intercommunication timing between FIFOA and FIFOB. Fig.22 gives an overview of pulse and timing of two cascaded FIFOs, when shifted full and shifted empty again.
Fig.19 Cascading for increased word capacity; 32 words x 4 bits.
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Product specification
4-bit x 16-word FIFO register
Notes to Fig.20
74HC/HCT40105
1. FIFOA and FIFOB initially empty, SOA held HIGH in anticipation of data. 2. Load one word into FIFOA; SI pulse applied, results in DIR pulse. 3. Data out A/data in B transition; valid data arrives at FIFOA output stage after a specified delay of the DOR flag, meeting data input set-up requirements of FIFOB. 4. DORA and SIB pulse HIGH; (ripple through delay after SIA LOW) data is unloaded from FIFOA as a result of the data output ready pulse, data is shifted into FIFOB. 5. DIRB and SOA go LOW; flag indicates input stage of FIFOB is busy, shift-out of FIFOA is complete. 6. DIRB and SOA go HIGH automatically; the input stage of FIFOB is again able to receive data, SO is held HIGH in anticipation of additional data. 7. DORB goes HIGH; (ripple through delay after SIB LOW) valid data is present one propagation delay later at the FIFOB output stage. Notes to Fig.21 1. FIFOA and FIFOB initially empty, SIB held HIGH in anticipation of shifting in new data as empty location bubbles-up. 2. Unload one word into FIFOB; SO pulse applied, results in DOR pulse. 3. DIRB and SOA pulse HIGH; (bubble-up delay after SOB LOW) data is loaded into FIFOB as a result of the DIR pulse, data is shifted out of FIFOA. 4. DORA and SIB go LOW; flag indicates the output stage of FIFOA is busy, shift-in to FIFOR is complete. 5. DORA and SIB go HIGH; flag indicates valid data is again available at FIFOA output stage, SIB is held HIGH, awaiting bubble-up of empty location.
(1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V.
(1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.20 FIFO to FIFO communication; input timing under empty condition.
6. DIRA goes HIGH; (bubble-up delay after SOA LOW) an empty location is present at input stage of FIFOA.
Fig.21 FIFO to FIFO communication; output timing under full condition.
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Product specification
4-bit x 16-word FIFO register
74HC/HCT40105
Fig.22 Waveforms showing the functionally and intercommunication between two FIFOs (refer to Fig.19).
Note to Fig.22 Sequence 1 (Both FIFOs empty, starting shift-in process): After a MR pulse has been applied FIFOA and FIFOB are empty. The DOR flags of FIFOA and FIFOB go LOW due to no valid data being present at the outputs. The DIR flags are set HIGH due to the FIFOs being ready to accept data. SOB is held HIGH and two SIA pulses are applied (1). These pulses allow two data words to ripple through to the output stage of FIFOA and to the input stage of FIFOB (2). When data arrives at the output of FIFOB, a DORB pulse is generated (3). When SOB goes LOW, the first bit is shifted out and a second bit ripples through to the output after which DORB goes HIGH (4). Sequence 2 (FIFOB runs full): After the MR pulse, a series of 16 SI pulses are applied. When 16 words are shifted in, DIRB remains LOW due to FIFOB being full (5). DORA goes LOW due to FIFOA being empty. Sequence 3 (FIFOA runs full): When 17 words are shifted in, DORA remains HIGH due to valid data remaining at the output of FIFOA. QnA remains HIGH, being the polarity of the 17th data word (6). After the 32th SI pulse, DIR remains LOW and both FIFOs are full (7). Additional pulses have no effect. 1998 Jan 23 19 Sequence 4 (Both FIFOs full, starting shift-out process): SIA is held HIGH and two SOB pulses are applied (8). These pulses shift out two words and thus allow empty locations to bubble-up to the input stage of FIFOB, and proceed to FIFOA (9). When the first empty location arrives at the input of FIFOA, a DIRA pulse is generated (10) and a new word is shifted into FIFOA. SIA is made LOW and now the second empty location reaches the input stage of FIFOA, after which DIRA remains HIGH (11). Sequence 5 (FIFOA runs empty): At the start of sequence 5 FIFOA contains 15 valid words due to two words being shifted out and one word being shifted in sequence 4. An additional series of SOB pulses are applied. After 15 SOB pulses, all words from FIFOA are shifted into FIFOB. DORA remains LOW (12). Sequence 6 (FIFOB runs empty): After the next SOB pulse, DIRB remains HIGH due to the input stage of FIFOB being empty (13). After another 15 SOB pulses, DORB remains LOW due to both FIFOs being empty (14). Additional SOB pulses have no effect. The last word remains available at the output Qn.
Philips Semiconductors
Product specification
4-bit x 16-word FIFO register
PACKAGE OUTLINES DIP16: plastic dual in-line package; 16 leads (300 mil); long body
74HC/HCT40105
SOT38-1
D seating plane
ME
A2
A
L
A1
c Z e b1 b 16 9 MH wM (e 1)
pin 1 index E
1
8
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.7 0.19 A1 min. 0.51 0.020 A2 max. 3.7 0.15 b 1.40 1.14 0.055 0.045 b1 0.53 0.38 0.021 0.015 c 0.32 0.23 0.013 0.009 D (1) 21.8 21.4 0.86 0.84 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.10 e1 7.62 0.30 L 3.9 3.4 0.15 0.13 ME 8.25 7.80 0.32 0.31 MH 9.5 8.3 0.37 0.33 w 0.254 0.01 Z (1) max. 2.2 0.087
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT38-1 REFERENCES IEC 050G09 JEDEC MO-001AE EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-10-02 95-01-19
1998 Jan 23
20
Philips Semiconductors
Product specification
4-bit x 16-word FIFO register
74HC/HCT40105
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A X
c y HE vMA
Z 16 9
Q A2 A1 pin 1 index Lp 1 e bp 8 wM L detail X (A 3) A
0
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 0.069 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 10.0 9.8 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.050 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 0.039 0.016 Q 0.7 0.6 0.028 0.020 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.7 0.3 0.028 0.012
0.010 0.057 0.004 0.049
0.019 0.0100 0.39 0.014 0.0075 0.38
0.244 0.041 0.228
8 0o
o
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07S JEDEC MS-012AC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-01-23 97-05-22
1998 Jan 23
21
Philips Semiconductors
Product specification
4-bit x 16-word FIFO register
74HC/HCT40105
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
D
E
A X
c y HE vM A
Z 16 9
Q A2 pin 1 index Lp L 1 bp 8 wM detail X A1 (A 3) A
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.0 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 6.4 6.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.00 0.55 8 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEDEC MO-150AC EIAJ EUROPEAN PROJECTION
ISSUE DATE 94-01-14 95-02-04
1998 Jan 23
22
Philips Semiconductors
Product specification
4-bit x 16-word FIFO register
74HC/HCT40105
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c y HE vMA
Z
16
9
Q A2 pin 1 index A1 Lp L (A 3) A
1
e bp
8
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.10 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1.0 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.40 0.06 8 0o
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC MO-153 EIAJ EUROPEAN PROJECTION ISSUE DATE 94-07-12 95-04-04
1998 Jan 23
23
Philips Semiconductors
Product specification
4-bit x 16-word FIFO register
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). DIP SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. REPAIRING SOLDERED JOINTS Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. SO, SSOP and TSSOP REFLOW SOLDERING Reflow soldering techniques are suitable for all SO, SSOP and TSSOP packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. 1998 Jan 23 24
74HC/HCT40105
Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. WAVE SOLDERING Wave soldering can be used for all SO packages. Wave soldering is not recommended for SSOP and TSSOP packages, because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering is used - and cannot be avoided for SSOP and TSSOP packages - the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end. Even with these conditions: * Only consider wave soldering SSOP packages that have a body width of 4.4 mm, that is SSOP16 (SOT369-1) or SSOP20 (SOT266-1). * Do not consider wave soldering TSSOP packages with 48 leads or more, that is TSSOP48 (SOT362-1) and TSSOP56 (SOT364-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
Philips Semiconductors
Product specification
4-bit x 16-word FIFO register
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
74HC/HCT40105
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1998 Jan 23
25

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